Because of the increasing complexity of integrated circuits (ICs) in general and photonic integrated circuits (PICs) in particular, the physical size and number of electrical connections required increases as well as the heat generated in devices of ICs. Excess heat needs to be effectively removed in order not to compromise performance of individual devices and consequently of the ICs to which they belong.
Conventional methods of providing electrical connections to a substrate that for example comprises a PIC, either using wire bonding techniques or flip chip bonding both present problems.
In the case of wire bonding, the length of wires as well as their density can seriously affect the performance and manufacturability of a device, either active or passive. Unlike in the case of standard electronic integrated circuits (EICs), in PICs the electrical connections can rarely be routed to the edges of the device to provide the necessary external onward connections to, e.g. associated terminals of a package. Moreover, on account of the design rules associated concerning wire length, which take into account the need for mechanical support during shock and vibration etc., it becomes difficult with large PICs to place wire bonds across the entire surface of the PIC. In addition high speed performance may also be compromised by the use of long wire bonds.
A technique often used for high electrical contact density EICs is known as flip chip bonding. In this method, each of the electrical contacts on the device is usually either made of solder or is solder coated or they are ‘stud bumped’ using a special machine very similar to a gold wire bonder that attaches a gold ball to the device contact. Flip chip bonding can be readily used also for sensors and other devices provided they are physically strong enough. This is usually the case if the devices are, for example, made of silicon (Si). However, the material for PICs usually comprises Indium Phosphide (InP), a material which lacks the mechanical strength of silicon. In the case of flip chip bonding, stresses created by the flip chip process and interconnect material and process can impair performance and reduce the thermal performance. Stress-induced damage can range from impairing the performance of the local waveguide of a PIC to mechanical breakage of the PIC.
When packaging devices and/or ICs, wire bonds are typically arranged between the device and an interconnect substrate of a chip package and subsequently between the interconnect substrate and at least one electrically conducting terminal of the chip package in order to maintain high-speed performance or meet design rules for wire bond lengths.
In order to enhance removal of excess heat from for example a packaged PIC, a thermoelectric cooler (TEC) can be arranged between the PIC and a housing of the chip package. Bond wires that are arranged between the interconnect substrate and the at least one electrically conducting terminal of the chip package provide a short thermal bridge and can reduce the efficiency of the TEC due to the thermal path conducting heat from the temperature controlled surface of the TEC to the ambient environment. If flip chip bonding were to be used, it could become difficult to extract the heat generated by the PIC through a relatively small area presented from the PIC through the bumps, which provide a poor thermal path to extract heat from the PIC. The problem of heat conduction is further aggravated by the generally small cross section of the bumps.